DDR (Double Data Rate) interface is widely used in memory systems of computing systems. As memory systems become faster and larger, they have become a heavy burden of power systems of computing systems, and the burden will be even heavier with the increasing operating speed and the capacity of the memory systems, and signal integrity will become an issue.
To address the issues mentioned above, the industry proposed fully buffered memory architectures such as FB-DIMM (Fully Buffered Dual In Line Memory Module) and LR-DIMM (Load-Reducing Dual In Line Memory Module). Each of such DIMMs has one or more buffers thereon to buffer data exchange between DRAMs (Dynamic Random Access Memory) on the DIMMs and a memory controller or a host. Each buffer provides a clock signal for read/write operations to the corresponding DRAMs using a multi-drop (fly-by) topology, so there will be phase difference between the clock signals received by different DRAMs due to different trace lengths. To ensure proper data transmission, each DRAM aligns its data signal (DQ) and a pair of data strobe signals (DQS/DQS#) with the received clock signal when sending the signals to the buffer, wherein DQS signal and DQS# signal are a pair of differential signals. But the phase relationship between the DQ/DQS/DQS# signals and the received clock signal may change with process, voltage, and temperature variations over time, leading to reduced timing margin for the buffer. The problem gets worse when data speed increases and even makes the buffer not being able to receive data correctly from the DRAMs. So conventionally, each DRAM incorporates a DLL (Delay Lock Loop) or PLL (Phase Lock Loop) to track the phase change of DQ/DQS/DQS# signals and maintain a fixed timing relationship between DQ/DQS/DQS# signals and the received clock signal, thus to ensure DQ/DQS/DQS# signals received by the buffer are covered by a read enable signal, which controls reading of DQ/DQS/DQS# signals by the buffer, on time axis, and thus to ensure proper transmission of the signals. However, since the DLLs are enabled to run whenever there is read/write operation, the power consumption of the DLLs is great, especially for memory systems with multi-rank (4, 8, or more) of DRAMs.
Therefore, it is necessary to provide a new method and a new memory system to solve the problems mentioned above.